Good Power Supply Rejection Ratio (PSRR) is an important performance metric for modern high performance linear regulators. While switched-mode DC-to-DC converters are usually preferred for their higher efficiencies, they have a relatively high output voltage ripple which makes them unsuitable for powering sensitive analog/RF circuitries, such as ADCs, DACs, PLLs, VCOs, etc.
An LDO regulator does not have any switching ripple so is commonly used for such analog circuits. An LDO regulator may receive as an input voltage a power supply voltage or an output of a switching voltage regulator whose output is slightly greater than the target voltage output from the LDO regulator.
As the switching frequencies of modem DC-DC converters increase to reduce the component sizes, to reduce the ripple peak-to-peak voltage, and to improve the transient performance, it is becoming increasingly difficult for LDO regulators to suppress the resulting higher frequency ripple since the high frequency may be beyond the bandwidth of the LDO regulator. While increasing the LDO regulator's bandwidth may improve its high frequency PSRR, it is rather difficult to achieve such a high bandwidth while maintaining loop stability over a wide range of operating conditions and output capacitor types, especially when a large power transistor is used in the LDO regulator.
Low dropout PNP bipolar transistor regulators offer a number of benefits which are difficult to replicate with NPN, NMOS, or PMOS transistor based linear regulators, such as reverse input protection, reverse current protection, reverse output protection, low dropout in single supply operation, and low minimum input voltage Vin.
To improve the PSRR in an LDO regulator, various techniques have been used in the prior art.
FIG. 1 illustrates cascoding the PNP bipolar power transistor 12 with a cascode transistor 14, biased by a voltage source 16, to increase the impedance between the input and output terminals of the LDO regulator. This improves PSRR but at the cost of higher dropout voltage and larger die area, as it requires two power transistors. An error amplifier 18 is used in a feedback loop to adjust the conductivity of the power transistor 12 so that the output voltage Vout matches a set voltage Vset, typically set by the user. A load is typically connected between Vout and ground.
FIG. 2 illustrates another approach using an NPN/NMOS based power transistor 20 to achieve better PSRR because its input impedance is inherently higher, its output impedance is inherently lower, and it has lower DC loop gain (thereby making it easier to achieve a higher bandwidth). But it also requires a higher dropout voltage or another supply rail to drive the NPN transistor's base current.
FIG. 3 illustrates stacking two LDO regulators (LDO1 and LDO2) in series, and independently controlling them, to improve PSRR. But this brute force approach requires an additional capacitor, doubles the circuit area, and increases the dropout voltage.
What is needed is an LDO regulator design that has very low dropout voltage, has a high bandwidth, has good PSRR, and achieves the improvement with a minimum of additional circuitry.